10 PCB faults that pass DRC and still cause a respin

Your PCB passed DRC with zero errors. The Gerbers look clean in the viewer. So the board is ready for fab, right? Not quite. DRC checks the rules you gave the tool. It has no idea what the board is meant to do. In design reviews we keep finding the same small group of faults on boards that passed every automated check. Each one is cheap to fix on screen and expensive to fix after the boards come back. Here are ten of them, with the quick check that catches each one. 1. The right part with the wrong suffix A regulator, an LDO or a MOSFET can come in fixed and adjustable versions, or in two packages, under nearly the same part number. The schematic symbol is drawn for one variant and the BOM orders the other. DRC can't see it because the footprint is fine. Check: read the full ordering code in the BOM against the datasheet ordering table. Every character, including the suffix. 2. Strap pins that float at power-up Many processors and wireless SoCs read a few pins at reset to choose the boot mode. If one of those pins also drives an LED or goes to a header, the boot mode depends on whatever else is on that net. The board boots on the bench and fails in the field. Check: list every strap pin from the datasheet. Confirm its level at reset with everything else on the net taken into account. 3. Land patterns copied from the wrong package A QFN from one vendor and a "compatible" part from another can differ in exposed pad size and pin 1 position. A generic library footprint looks right in 3D and still solders badly. Check: compare pad size, pitch, pin 1 and the thermal pad against the recommended land pattern in the datasheet of the exact part you are ordering. 4. A fast signal crossing a plane split The trace is fine. The return current is not. When a clock or a high-speed line crosses a gap in its reference plane, the return path takes a long detour. That shows up as emissions and noise that are very hard to debug later. Check: turn on the reference plane under each fast net and follow the trace. Any crossing of a split, slot or void needs a stitching capacitor or a reroute. 5. A switching regulator hot loop that grew during routing The layout guide shows the input capacitor right next to the switch. Then a connector moved, the capacitor moved with it and the loop doubled in area. Nothing fails DRC. The rail rings and the EMI scan fails. Check: highlight the input capacitor, the switch node and the ground return. Compare the loop area to the reference layout in the datasheet. 6. Impedance traces that don't match the fab's stackup The trace width was set from a calculator using a generic stackup. The fab builds with different prepreg and the impedance lands outside tolerance. Check: get the stackup from your fab first and size controlled-impedance traces from their numbers. Put the targets and tolerance on the fab drawing. 7. DRC run with tool defaults The default rule set in most EDA tools is not your fab's capability. Minimum annular ring, drill to copper and mask expansion all vary by fab and by price tier. Check: load the fab's published rules into the tool before the final DRC. Keep the rule file in the project. 8. MLCC capacitance measured at 0 V A 10 uF 0603 capacitor at 5 V DC bias can deliver a fraction of its rated value. The regulator loop was designed around the full 10 uF. Check: look up the DC bias curve for each bulk MLCC at the real working voltage. Size up the case or add parts if needed. 9. Connector orientation that only works in 2D The connector is placed correctly on the board. In the enclosure the cable has to bend 180 degrees to reach it, or the latch faces a wall. Check: check mating side, latch direction and cable exit against the enclosure model or the mechanical drawing, not only the PCB view. 10. Output files that don't match the design of record A late ECO changed the schematic. The netlist and BOM in the release folder are from the day before. The fab builds what you sent, not what you meant. Check: regenerate every output from the same revision. Confirm the revision text on copper or silkscreen matches the file names and release notes. Use a checklist, at three gates None of these checks is hard. They get skipped because they happen at the end, under time pressure, by the same person who drew the board. Two things help. First, run reviews at three gates instead of one: schematic freeze, after placement and before release. Most of the items above are much cheaper to catch at the first two gates. Second, rank findings. A Critical finding means the board won't work or can't be built. A Major finding means it might work on the bench but will likely need a respin. A Minor finding is documentation or style. Release only with zero open Critical and Major items. We published our full 42-point list as a free, open checklist on GitHub so you can copy it into your own release process: PCB design review checklist on GitHub. It comes as Markdown and CSV under CC BY 4.0. The longer write-up with the reasoning behind each check is on our blog: PCB design review checklist: the checks we run before fab. If your board is part of a product moving from prototype to production, the review gates map well onto EVT, DVT and PVT builds. This guide explains what each build should prove: EVT, DVT and PVT explained. Circuit Board Design is the PCB design division of Electuni LLC, a US company founded in 2016. We have delivered 500+ PCB designs and our lead designer is IPC CID+ certified. If you want a second set of eyes before fab, we offer a free quick design check.